datasheet low phase noise vcxo and multiplier mk2732-06 idt? low phase noise vcxo and multiplier 1 mk2732-06 rev h 051310 description the mk2732-06 is a low-cost, low-jitter, high-performance vcxo and pll clock synthesizer designed to replace expensive discrete vcxos and multipliers. the on-chip voltage controlled crystal osc illator (vcxo) accepts a 0 to 3 v input voltage to cause the output clocks to vary by 100 ppm. using idt?s patented vcxo and analog phase-locked loop (pll) techniques, the device uses an inexpensive 10 mhz to 14 mhz pullable crystal input to produce up to three output clocks. idt manufactures the largest variety of clocks for set-top boxes and communications. consult idt to eliminate vcxos, crystals, oscillators andbuffers from your board. features ? packaged in 16-pin tssop ? pb (lead) free package ? for xdsl chipsets ? for mpeg2 decoders ? replaces vcxo and multiplier ? uses an inexpensive pullable crystal ? on-chip patented vcxo with pull range of 200 ppm (100 ppm) minimum ? vcxo tuning voltage of 0 to 3 v ? zero ppm synthesis error in all clocks ? full cmos output swings with 25 ma output drive capability at ttl levels ? advanced, low-power, sub-micron cmos process ? 5 v operating voltage for core, ability to run output clocks at 3.3 v or 5 v for easy interface. ? available in commercial and industrial temperature versions block diagram clk1 pll/clock synthesis circuitry x1 x2 10 - 14 mhz pullable crystal voltage controlled crystal oscillator vdd5 vin clk2 refclk oe (all outputs) s1, s0 2 vddio
mk2732-06 low phase noise vcxo and mult iplier vcxo and synthesizer idt? low phase noise vcxo and multiplier 2 mk2732-06 rev h 051310 pin assignment clock select table 0 = connect directly to ground m=leave unconnected (floating) 1 = connect directly to vddio off=output stopped low pin descriptions key: ti = tri-level input; vi = analog voltage input; xi, xo = crystal pins 1 2 3 gnd 4 vdd5 5 6 refclk 7 8 nc gnd s0 s1 x2 gnd clk1 vdd5 16 x1 vin oe vddio clk2 15 14 13 12 11 10 9 16-pin (173 mil) tssop s1 s0 input clk1 clk2 refclk 0 0 13.248 52.992 35.238 off 0 m 13.248 13.248 35.238 off 0 1 13.248 13.248 35.238 on m 0 13.248 52.992 35.238 on m m 13.5 54 27 off m113.554 27on 1013.527 54on 1 m test mode ? ? ? 1113.527 27on pin number pin name pin type pin description 1 x1 xi crystal connection. connect to a pullable crystal of 10 to 14.318 mhz. 2 , 3 vdd5 power core vdd. connect to +5 v. 4 vin vi voltage input to vcxo. zero to 3 v signal which controls the frequency of the vcxo. 5, 6, 13 gnd power connect to ground. 7 s1 ti select input #1. selects the outputs per table above. do not exceed vddio. 8 oe input output enable. tri-states outputs when low. do not exceed vddio. 9 clk1 output clock output #1 per table above. amplitude = vddio. 10 s0 ti select input #0. selects the outputs per table above. do not exceed vddio. 11 vddio power input and output vdd. connect to 3.3. v or 5 v. clock amplitude matches this voltage. 12 clk2 output clock output #2 per table above. amplitude = vddio. 14 nc ? nothing connected internally to this pin. 15 refclk output buffered crystal vcxo clock. 16 x2 xo crystal connection. connect to a pullable crystal of 10 to 14 mhz.
mk2732-06 low phase noise vcxo and mult iplier vcxo and synthesizer idt? low phase noise vcxo and multiplier 3 mk2732-06 rev h 051310 external component selection the mk2732-06 requires a minimum number of external components for proper operation. decoupling capacitor a decoupling capacitor of 0.01 f and 0.1 f must be connected between vdd5 and gnd on pins 2, 3 and 5, 6, and vddio and gnd on pins 11 and 13, as close to the device as possible. for optimum device performance, the decoupling capacitor should be mounted on the component side of the pcb. avoid the use of vias in the decoupling circuit. series termination resistor when the pcb trace between the clock outputs and the loads are over 1 inch, series termination should be used. to series terminate a 50 ? trace (a commonly used trace impedance) place a 33 ? resistor in series with the clock line, as close to the clock output pin as possible. the nominal impedance of the clock output is 20 ? . quartz crystal the mk2732-06 vcxo function consists of the external crystal and the integrated vcxo oscillator circuit. to assure the best system performance (frequency pull range) and reliability, a crystal de vice with th e recommended parameters (as described in application note man05) must be used, and the layout guidelines discussed in the following section must be followed. the frequency of oscilla tion of a quartz crystal is determined by its ?cut? and by the load capacitors connected to it. the mk2732-06 incorporates on-chip variable load capacitors that ?pull? (change) the frequency of the crystal. the crystal specified for use with the mk2732-06 is designed to have zero frequency error when the total of on-chip + stray capacitance is 14 pf. the external crystal must be connected as close to the chip as possible and should be on the same side of the pcb as themk2732-06. there should be no vias between the crystal pins and the x1 and x2 device pins. there should be no signal traces underneath or close to the crystal. crystal tuning load capacitors the crystal traces should include pads for small fixed capacitors, one between x1 and ground, and another between x2 and ground. stuffing of these capacitors on the pcb is optional. the need for these capacitors is determined at system prototype evaluation, and is influenced by the particular crystal used (manufacture and frequency) and by pcb layout. the typical required capacitor value is 1 to 4 pf. to determine the need for and value of the crystal adjustment capacitors, you will ne ed a pc board of your final layout, a frequency counter capable of about 1 ppm resolution and accuracy, two power supplies, and some samples of the crystals which you plan to use in production, along with measured initial accuracy for each crystal at the specified crystal load capacitance, c l . to determine the value of the crystal capacitors: 1. connect vdd of the mk2732 -06 to 3.3 v. connect pin 3 of the mk2732-06 to the second power supply. adjust the voltage on pin 3 to 0v. measure and record the frequency of the clk output. 2. adjust the voltage on pin 3 to 3.3 v. measure and record the frequency of the same output. to calculate the centering error: where: f target = nominal crystal frequency error xtal =actual initial accuracy (in ppm) of the crystal being measured if the centering error is less than 25 ppm, no adjustment is needed. if the centering error is more than 25 ppm negative, the pc board has excessive stray capacitance and a new pcb layout should be considered to reduce stray capacitance. (alternately, the crystal may be re-specified to a higher load capacitance. contact idt for details.) if the centering error is more than 25 ppm positive, add identical error 10 6 x f 3.0v f tet arg ? () f 0v f tet arg ? () + f tet arg ------------------------------------------------------------------------------ error xtal ? =
mk2732-06 low phase noise vcxo and mult iplier vcxo and synthesizer idt? low phase noise vcxo and multiplier 4 mk2732-06 rev h 051310 fixed centering capacitors from each crystal pin to ground. the value for each of these caps (in pf) is given by: external capacitor = 2 x (centering error)/(trim sensitivity) trim sensitivity is a parameter which can be supplied by your crystal vendor. if you do not know the value, assume it is 30 ppm/pf. after any changes, repeat the measurement to verify that the remaining error is acceptably low (typically less than 25 ppm). absolute maximum ratings stresses above the ratings listed below can cause permanent damage to the mk2732-06. these ratings, which are standard values for idt commercially rated parts, are stress ratings only. functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for exte nded periods can affect product reliability. electrical parameters are guaranteed only over the recommended operating temperature range. recommended operation conditions item rating supply voltage, vdd 7 v all inputs and outputs -0.5 v to vdd+0.5 v ambient operating temperature, commercial version 0 to +70 c ambient operating temperature, industrial version -40 to +85 c storage temperature -65 to +150 c junction temperature 125 c soldering temperature 260 c parameter min. typ. max. units ambient operating temperature 0 +70 c power supply voltage (measured in respect to gnd) +4.75 +5.25 v reference crystal parameters refer to man05
mk2732-06 low phase noise vcxo and mult iplier vcxo and synthesizer idt? low phase noise vcxo and multiplier 5 mk2732-06 rev h 051310 dc electrical characteristics unless noted otherwise, vdd5=5.0 v, vddio=3.3 v , ambient temperature 0 to +70 c parameter symbol conditions min. typ. max. units core operating voltage vdd5 4.75 5.0 5.25 v operating voltage vddio 3.13 3.3 5.25 v operating supply current idd no load 11 ma operating supply current iddio no load 5 ma input high voltage v ih x1 pin only 3.5 2.5 v input low voltage v il x1 pin only 2.5 1.5 v input high voltage v ih binary input, oe 2 v input low voltage v il binary input, oe 0.8 v input high voltage v ih trinary inputs, s1, s0 vdd-0.5 v input low voltage v il trinary inputs, s1, s0 0.5 v output high voltage v oh i oh = -25 ma 2.4 v output low voltage v ol i ol = 25 ma 0.4 v output high voltage v oh cmos level, i oh = -8 ma vdd-0.4 v short circuit current each output 50 ma input capacitance c in s1, s0, oe 7 pf frequency synthesis error all clocks 0 ppm vin, vcxo control voltage 0 3 v
mk2732-06 low phase noise vcxo and mult iplier vcxo and synthesizer idt? low phase noise vcxo and multiplier 6 mk2732-06 rev h 051310 ac electrical characteristics unless noted otherwise, vdd5=5.0 v, vddio=3.3 v , ambient temperature 0 to +70 c parameter symbol conditions min. typ. max. units crystal input frequency f in 10 14 mhz output rise time t or 0.8 v to 2.0 v 1.5 ns output fall time t of 2.0 v to 0.8 v 1.5 ns output clock duty cycle at vddio/2 40 60 % maximum absolute jitter, short term 150 ps phase noise, relative to carrier 10 khz offset -115 dbc/hz output pullability 0v < vin < 3 v 100 ppm
mk2732-06 low phase noise vcxo and mult iplier vcxo and synthesizer idt? low phase noise vcxo and multiplier 7 mk2732-06 rev h 051310 package outline and package dimensions (16-pin tssop, 173 mil. body) package dimensions are kept current with jedec publication no. 95 ordering information while the information presented herein has been checked for both ac curacy and reliability, integrat ed device technology (idt) a ssumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or licenses are implied. this product is intended for us e in normal commercial applications. any ot her applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommen ded without additional pr ocessing by idt. i dt reserves the right to change any circuitry or specificat ions without notice. idt does not authorize or warrant any idt product for use in life suppor t devices or critical medical instruments. part / order number marking shipping packaging package temperature mk2732-06glf 27326lf tubes 16-pin tssop 0 to 70 c mk2732-06glftr tape and reel 16-pin tssop 0 to 70 c MK2732-06GIlf 27326ilf tubes 16-pin tssop -40 to 85 c MK2732-06GIlftr tape and reel 16-pin tssop -40 to 85 c index area 1 2 16 d e1 e seating plane a1 a a2 e - c - b aaa c c l millimeters inches symbol min max min max a--1.20--0.047 a1 0.05 0.15 0.002 0.006 a2 0.80 1.05 0.032 0.041 b 0.19 0.30 0.007 0.012 c 0.09 0.20 0.0035 0.008 d 4.90 5.1 0.193 0.201 e 6.40 basic 0.252 basic e1 4.30 4.50 0.169 0.177 e 0.65 basic 0.0256 basic l 0.45 0.75 0.018 0.030 0 8 0 8 aaa -- 0.10 -- 0.004
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